(a) Field of the Invention
The invention relates to a memory device, particularly to a memory device having a shared redundancy decision scheme.
(b) Description of the Related Art
The shared redundancy decision scheme for a conventional memory device 10 is shown in FIG. 1A that needs two sets of shared redundancy decision circuits, one of which is a row decision circuit Dec1 and the other of which is a column decision circuit Dec2.
The row decision circuit Dec1 comprises an address receiver 101, a row address generator 104, a row redundancy decision circuit 106, a normal word line controller 108, normal word lines NWL, a redundancy word line controller 109, and redundancy word lines RWL while the column decision circuit Dec2 comprises a command receiver 102, a command controller 103, a column address generator 105, a column redundancy decision circuit 107, a normal bit switch controller 110, normal bit switches NBS, a redundancy bit switch controller 111, redundancy bit switches RBS.
Please refer to FIGS. 1A and 1B simultaneously. As the conventional memory device 10 is in operation, the address receiver 101 receives external address information XADD to generate internal address information ADD and then output the internal address information ADD to the row address generator 104 or the column address generator 105. The command receiver 102 receives an external command XCMD to generate an internal command CMD and then the command controller 103 decides how to generate a row latch control signal RLAT or a column latch control signal CLAT to control the row address generator 104 or the column address generator 105 based on the internal command CMD so as to generate a latched row address ADD_ROW or column address ADD_COL. As shown in FIG. 1B, from the time t1 completing processing the external address information XADD to the time t2 deciding the latched address ADD_ROW or ADD_COL, the conventional memory device 10 takes the time length T1.
According to the design in the prior art, the row or column redundancy decision circuit 106 or 107 has to receive the latched row or column address ADD_ROW or ADD_COL outputted by the row address generator 104 or the column address generator 105 at the time t2 and then can decide whether to set the generated row redundancy start signal RHIT or the generated column redundancy start signal CHIT to enable (logic 1) or disable (logic 0) to start the part of the normal circuits or the redundancy circuits at the time t3 based on the latched row or column address ADD_ROW or ADD_COL. Therefore, as shown in FIG. 1B, the row or column redundancy decision circuit 106 or 107 of the conventional memory device 10 takes the time length T2 for the redundancy decision.
It should be noted, even if the latched row or column address ADD_ROW or ADD_COL are transmitted to the word line controller 108, 109 or to the bit switch controller 110, 111, the data in the conventional memory device 10 cannot be accessed until the decision operation on the normal circuits and the redundancy circuits by the row or column redundancy decision circuit 106 or 107 is completed. Therefore, it takes time and greatly reduces the processing speed.